Field of the Invention
The disclosure relates generally to a DC-DC switching power converter, employing dead time in the ON/OFF timings of high and low side devices at the output of the converter.
Description of Related Art
Synchronous switching converters employ high and low side switches. It is a design precaution that these switches should never be ON at the same time, or a short circuit condition may occur. Even though there is no short circuit condition, there may be a shoot-through current case, which causes inefficiency in the switching converter. Thus when changing switch states, switching converters employ a break before make condition, where both high and low side switches are off, commonly called dead time. This occurs between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the low-side switch conducts the output current, and both switches are simultaneously turned on. This can also occur between the turn-off of the low-side switch and the turn-on of the high-side switch, when the body diode of the high-side switch conducts the output current, and both switches are simultaneously turned on. During dead time, coil current flows through the body diode of the switches, resulting in an efficiency loss of up to 5 to 7%.
One technique of the prior art employs pass device gate voltages as feedback information for non-overlapping time, and targets to match pass device gate voltage transients. This scheme is not very effective, as it does not guarantee that short circuit does not occur. The technique is sensitive to delay mismatch across process, temperature, voltage, and parasitic capacitances in the design, and it does not guarantee a minimum dead time.
Another technique of the prior art makes use of an operational transconductance amplifier based comparator, to detect body diode conduction and logic circuitry to end dead time after detection. This technique is not efficient, as the delays associated with the comparator, logic cells, and drivers contribute to significant delay time, resulting in slow response of the circuit and efficiency loss.